Accelerated switching input circuit

ABSTRACT

An accelerated switching input circuit includes an emitter coupled logic stage having two transistors. The first transistor receives at its base an input signal and the second transistor receives at its base a control signal generated from the signal at the collector of the first transistor. A third transistor (T 6 ) has its base connected to the collector of the first transistor (T 3 ). A first resistor (R 10 ), a second resistor (R 11 ) and a third resistor (R 12 ) are disposed in series between the emitter of the third transistor and a reference voltage (U REF ) source. The point B common to the resistors R 11  and R 12  is coupled to the base of the second transistor (T 4 ).

BACKGROUND OF THE INVENTION

The invention relates to a switching input circuit having a stage of theemitter coupled logic (ECL) type having two transistors, the firstreceiving on its base an input signal and the second receiving on itsbase a control signal which is generated by a control circuit from thesignal from the collector of the first transistor, in order to obtain onthe collector of the second transistor an output signal switching fasterthan the input signal.

Such a circuit, generally used in order to compensate for the slowingdown in switching due to highly capacitive input lines, is known fromthe MOTOROLA publication "Microelectronic Cell Data Book", the controlsignal consisting of a simple resistive divider bridge between thecollector of the first transistor, the base of the second transistor andground. When, for example, the voltage E changes from a low state to ahigh state, the putting into conduction of the first transistor causesthe lowering of the voltage on the base of the second transistor, whichaccelerates the switching. This phenomenon is the same, in the oppositedirection, for a transition of the signal E from a high state to a lowstate. The direct dependence between the control voltage and the signalfrom the collector of the first transistor means that it is not possibleto select all of the operating parameters.

SUMMARY OF THE INVENTION

The present invention proposes an input circuit of the abovementionedtype in which the value and the amplitude of the control voltage can beselected.

The circuit according to the invention is, for this purpose,characterized in that the control circuit comprises a third transistorwhose collector is connected to a voltage supply source, whose base isconnected to the collector of the first transistor and in that itsuccessively comprises a first resistor, a second resistor and a thirdresistor disposed in series between the emitter of the third transistorand a reference point to which are connected a reference voltage sourceand a first reference current source, the point common to the firstresistor and the second resistor being connected to a second referencecurrent source, and the point common to the second resistor and thethird resistor supplying the said control signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood on reading the followingdescription with reference to the single figure which shows thepreferred embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The circuit comprises an input follower stage comprising a transistor T₁receiving on its base input signals e, and producing on an emittersignals E, this emitter being connected in a conventional way to acurrent source (T₂, R₂). This buffer stage is conventional and has onlyan optional decoupling function. The actual input circuit comprises agate of the emitter coupled logic (ECL) type comprising two transistorsT₃ and T₄ whose coupled emitters are connected to a current source (R₅,T₅) of value I₁. The collectors of transistors T₃ and T₄ are connectedto a voltage supply source V_(c) via the resistors R₃ and R₄respectively. The base of the transistor T₃ receives the signal E fromthe first emitter of the transistor T₁. The output signal S is thesignal supplied by the collector of the transistor T₄, the collector ofthe transistor T₃ supplying the complementary signal S.

The base voltage of the transistor T₄ is determined by the collectorvoltage of the transistor T₃. With regard to the prior art, it hasalready been mentioned that this was performed by potentiometricdivision of the collector voltage of the transistor T₃. The disadvantageof this is to considerably limit the control of the effect thusproduced. It is thus possible to select the central value of the basevoltage of the transistor T₄, but at that time, the amplitude of itsvariation cannot be selected. On the other hand, if it is desired toselect the amplitude of this variation, then the central value cannot beselected and, in any case, the value of this amplitude is limited to afraction of the switching amplitude ΔV of the ECL gate.

The circuit which will now be described enables both parameters to beselected and furthermore to be selected within a range of values as wideas desired.

The base of a transistor T₆ is connected to the collector of thetransistor T₃. The collector of the transistor T₆ is connected to asupply voltage V_(c), and its emitter is connected to a point C viathree resistors in series, R₁₀, R₁₁, and R₁₂ respectively, a forwardbiased diode T₁₀ possibly being interposed between the emitter of thetransistor T₁₀ and the resistor R₁₀ in order to perform a levelcompensation. The point A which is common to the resistors R₁₀ and R₁₁is connected to a current source (R₈, T₈) of value I_(c). The point Bwhich is common to the resistors R₁₁ and R₁₂ is connected to the base ofthe transistor T₄, possibly via a resistor R₄. The abovementioned pointC, at the other end of the resistor R₁₂, is connected to a referencevoltage source U_(REF). This reference voltage source comprisestransistor T₇ whose collector is connected to the supply voltage sourceV_(c), whose base receives a reference voltage (V_(c) -V_(REF)), and ofwhich an emitter is connected to the point C and to a current source(R₉, T₉) of value I_(D). This current I_(D) ensures, in particular, thata current I_(r) always flows through the said emitter such that thefollowing is always true:

    U.sub.REF =V.sub.c -V.sub.REF -V.sub.BE

V_(BE) denoting the base-emitter voltage of a transistor, i.e.approximately 0.7 V.

Three principal states can be distinguished. When the input signal E isat the low level (first state), the transistor T₃ is cut off and thecollector of the transistor T₃ is at the voltage V_(c). When the signalE is at the high level (second state), the transistor T₃ is conductingand the collector of the transistor T₃ is at the voltage V_(c) -ΔVwhere:

    ΔV=R.sub.3 I.sub.1

This value ΔV of the switching amplitude is fixed by the standardsdefining the circuit (800 mV for ECL).

The third state is a state of transient equilibrium.

In the first state (E at the low level), the voltage on the emitter ofthe transistor T₁₀ (point 0) is at the high level which is higher thanthe voltage at the point C and the entire current I_(c) passes throughthe resistor R₁₀. In the second state (E at the high level), the voltageat the point D is at the low level which is lower than the voltage atthe point C, the voltage at the point A is lower than that at the pointC and the current I_(c) is divided between the two branches R₁₀ and(R₁₁, R₁₂). This is what enables an adjustment to be performed on theamplitude of the voltage variation on the base of the transistor T₄ andtherefore the use of the input circuit for different values of ΔV. Inthe third state, the voltages at the point A and at the point C areequal, there is no current in the branch (R₁₁, R₁₂) and the voltage atthe point B therefore has the value U_(REF) which must, for symmetricaloperation, be equal to the value E₀ of the input signal E at mid-slope.

In this case the following is true:

    E.sub.0 =U.sub.REF =V.sub.c -V.sub.REF -V.sub.D

from which the value of V_(REF) is derived

    V.sub.REF =V.sub.c -V.sub.D -E.sub.0

There will now be described a method of calculating the components ofthe circuit which will enable a symmetrical operation to be obtained.

For a symmetrical operation, the circuit is chosen to be in the thirdstate for a switching half-amplitude, i.e.:

    S=V.sub.c -ΔV/2

The equation of equilibrium is therefore written:

    V.sub.c -ΔV/2-V.sub.D -V.sub.BE6 -R.sub.10 I.sub.c =U.sub.REF =V.sub.c -V.sub.REF -V.sub.BE7

where

V_(D) is the voltage drop in a diode

V_(BE6) is the base-emitter voltage of the transistor T₆

V_(BE7) is the base-emitter voltage of the transistor T₇.

As the currents passing through the transistors T₆ and T₇ arerespectively I_(c) and I_(D), (I_(r) =I_(D)), the first condition isobtained:

    R.sub.10 I.sub.c =V.sub.REF -ΔV/2-V.sub.D +V.sub.T Log I.sub.D /I.sub.c                                                  (1)

It is advantageous to choose I_(c) =I_(D), giving:

    R.sub.10 I.sub.c =V.sub.REF -ΔV/2-V.sub.D            (2)

giving:

    R.sub.10 I.sub.c =V.sub.c -2V.sub.D -E.sub.o -ΔV/2   (2')

In the first state, the following is true (writing the equation ofvoltage at the point A)

    V.sub.c -(V.sub.BE6 +V.sub.D +I.sub.10 R.sub.10)=V.sub.c -V.sub.REF -V.sub.BE7 +I.sub.11 (R.sub.11 +R.sub.12)

I₁₁ denoting the current passing through the resistors R₁₁ and R₁₂.Giving V_(BE6) +V_(D) +I₁₀ R₁₀, +I₁₁ (R₁₁ +R₁₂)=V_(REF) +V_(BE7) and I₁₀=I_(c) +I₁₁ ; I₁₁ +I_(R) =I_(D) from which:

    V.sub.BE6 +V.sub.D +(I.sub.c +I.sub.D -I.sub.R)R.sub.10 +(I.sub.D -I.sub.R) (R.sub.11 +R.sub.12)=V.sub.REF +V.sub.BE7

As the transistors T₆ and T₇ have currents flowing through them whichare respectively equal to I_(c) +I_(D) -I_(R) and I_(R), the secondcondition is obtained. ##EQU1##

The ratio n can be selected between I_(D) and I_(R), for example equalto 2.

The following is then true for n=2 and I_(c) =I_(D) ##EQU2## In thesecond state, the current I₁₁ flows in the other direction and thecurrent I_(C) is divided between R₁₀ on the one hand and R₁₁ and R₁₂ onthe other hand:

    V.sub.c -ΔV-(V.sub.BE6 +V.sub.D +I.sub.10 R.sub.10)=V.sub.c -V.sub.REF -V.sub.BE7 -I.sub.11 (R.sub.11 +R.sub.12)

or:

    ΔV+V.sub.BE6 +V.sub.D +I.sub.10 R.sub.10 =V.sub.REF +V.sub.BE7 +I.sub.11 (R.sub.11 +R.sub.12)

    I.sub.10 +I.sub.11 =I.sub.c

    I.sub.R =I.sub.D +I.sub.11

giving: ##EQU3## where I_(R) has a value different from that in thefirst state.

The relationship I₁₁ =(I_(c))/2 is chosen, giving the third condition:##EQU4## or with I_(c) =I_(D), ##EQU5##

The following expression is obtained on bringing together the equations(4) and (6'):

    (R.sub.10 +R.sub.11 +R.sub.12)I.sub.c =ΔV-2V.sub.T Log3(7)

Using equation (2'), the following is obtained:

    (R.sub.11 +R.sub.12)I.sub.c =3/2ΔV-2V.sub.T Log3-V.sub.c +2V.sub.D +E.sub.o                                                  (8)

The equations (2') and (8) enable the values of the components of theinput circuit to be selected as a function both of the switchingamplitude ΔV of the emitter coupled logic stage and of the centralswitching value E_(o) on the base of the transistor T₃.

It is furthermore possible to select the value of the deviation |V_(B)-E_(O) | in the first and second states. This deviation is the same inboth these states as a symmetrical function has been chosen (see above).

The following is true in the first state: ##EQU6##

Replacing R₁₀ I_(c) by its value taken from (2'), and replacing V_(c)-E_(O) by V_(REF) +V_(D) the following is obtained: ##EQU7##

By selecting the value of R₁₁ I_(c), the value of |V_(B) -E_(O) | isselected and therefore the amplitude of the control signal. Example:

V_(REF) =1.3 V

ΔV=600 mV

I_(c) =I_(D) =250 μA

V_(D) =0.75 V

R₁₀ =1 kohm

R₁₁ =R₁₂ =500 ohms

|V_(B) -E_(O) |=112.5 mV

I claim:
 1. Switching input circuit comprising: a stage of the emittercoupled logic (ECL) type having first and second transistors, the firsttransistor receiving at its base an input signal and the secondtransistor receiving at its base a control signal which is generated bya control circuit responsive to a signal from a collector of the firsttransistor, in order to obtain at a collector of the second transistoran output signal switching faster than the input signal, wherein thecontrol circuit comprises a third transistor whose collector isconnected to a voltage supply source and whose base is connected to thecollector of the first transistor, a first resistor, a second resistorand a third resistor connected in series between an emitter of the thirdtransistor and a reference point to which is connected a referencevoltage source and a first reference current source, means connecting apoint common to the first resistor and the second resistor to a secondreference current source, and a point common to the second resistor andthe third resistor supplying said control signal and being connected tothe base of the second transistor.
 2. A circuit according to claim 1,wherein the reference voltage source comprises a fourth transistor whosecollector is connected to the voltage supply source and whose base isconnected to a reference voltage.
 3. A circuit according to claim 2,which comprises at least one forward biased diode connected between theemitter of the third transistor (R₁₀) and the first resistor (R₁₀).
 4. Acircuit according to claim 1, which comprises at least one forwardbiased diode connected between the emitter of the third transistor andthe first resistor.